(1) Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and its control method, and in particular relates to a nonvolatile semiconductor storage device which enables electric writing and erasing of data and its control method.
(2) Description of the Prior Art
Conventionally, in the access scheme for nonvolatile semiconductor storage devices enabling electric writing and erasing of data, typically represented by flash memories, data reading is performed by using a dedicated control terminal or terminals, as is performed by a volatile memory such as a DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) or a non-volatile memory such as ROM (Read only Memory). On the other hand, concerning data writing and erasing of memory cells, usually no dedicated control terminal is provided, but commands indicating data writing and erasing operations are input externally to perform the necessary operation, instead.
Such a data erasing and programming (data writing) method based on command control for use in an electrically rewritable and erasable nonvolatile semiconductor storage device has been disclosed in detail by Japanese Patent Publication Hei 6 No.32226.
As in Japanese Patent Publication Hei 6 No.32226, an input command is usually constructed of multiple cycles accompanying activation of each chip enable signal, such as set-up erase and erase commands.
Referring now to FIG. 1, circuit blocks in a typical nonvolatile semiconductor storage device will be described. FIG. 2 shows a flowchart for illustrating the internal operation of this circuit configuration when write operations are performed in succession. The nonvolatile semiconductor storage device shown in FIG. 1 has the same structure as that of the nonvolatile semiconductor storage device according to the first embodiment of the present invention to be detailed hereinbelow.
In FIG. 2, though only data write operations are described, the internal operation when a data erase operation is performed is equivalent to that shown in FIG. 2 except that xe2x80x98writexe2x80x99 is replaced by xe2x80x98erasexe2x80x99.
As shown in FIG. 1, the conventional nonvolatile semiconductor storage device is comprised of a nonvolatile memory cell array 10 made up of a multiple number of memory cell transistors (not shown), a write/erase control circuit 20, an internal charge pump circuit 30 and a command user interface 40 for interpreting the commands input externally.
Interval charge pump circuit 30 is a circuit which pumps the voltage supplied externally to such a level as to be able to change the threshold of the memory cell transistors in nonvolatile memory cell array 10 (so as to be able to perform data writing or data erasing).
Write/erase control circuit 20 is a circuit for making the write/erase in-process status signal active based on a write/erase command input signal through command user interface 40 so as to indicate that a write operation or erase operation has started (has been in progress) and actuating the operation of internal charge pump circuit 30 by making active the actuating signal to internal charge pump circuit 30 in order to obtain the necessary voltage for implementing the write/erase operation of the memory cell (for changing the threshold of the memory cell transistor).
Write/erase control circuit 20, in response to the pumping-complete signal from internal charge pump circuit 30, performs the write/erase operation to nonvolatile memory cell array 10, using the pumping write/erase voltage. When a write/erase operation has been completed, the actuating signal for internal charge pump circuit 30 output from write/erase control circuit 20 is made inactive so as to stop the operation of internal charge pump circuit 30 while the write/erase in-process status signal is made inactive to thereby indicate that the write or erase operation has been completed.
In the nonvolatile semiconductor storage device having the above circuit configuration, once a write command is input to the nonvolatile semiconductor storage device (S1), write/erase control circuit 20 turns on internal charge pump circuit 30 (S2), as shown in FIG. 2.
Then, internal charge pump circuit 30 starts the pumping operation and continues it until the pumping reaches a specified voltage (S3). When the specified voltage has been reached, the pumping-complete signal is returned to write/erase control circuit 20 (S4).
Subsequently, write/erase control circuit 20 implements writing of data into nonvolatile memory cell array 10, using the pumping voltage (S5).
When the write operation has been completed, internal charge pump circuit 30 is turned off (S6). That is, the pumping voltage is reduced and the waiting mode is restored so as to be able to accept a new command to implement (S7).
When another write command is input in succession, the same operation will be started once again (S1 to S7).
Up to now, the internal operation for data writing has been described, but the internal operation for data erasing is also performed in the same sequence as above. In this case, the internal operation for data erasing is equivalent to that shown in FIG. 2 where xe2x80x98writexe2x80x99 is replaced by xe2x80x98erasexe2x80x99.
Since the conventional nonvolatile semiconductor storage device is thus configured, it includes the following problems.
In the conventional nonvolatile semiconductor storage device, if write commands or erase commands are input in succession, internal charge pump circuit 30 performs the pumping-off operation every end of write or erase operation. This is because the conventional nonvolatile semiconductor storage device has no means for distinguishing the relationship between the command being currently implemented and the command to be input next. Further, since a different pumping voltage is needed for a different command, the charge pump circuit needs to be initialized in preparation for a next input of a different command.
Incidentally, nonvolatile semiconductor storage devices, typified by flash memories, have usually been used as rewritable read only memory after they have been mounted on product boards. Therefore, the above configuration did not pose any inconvenience.
However, with the recent development of flash memories into large capacities, their improvement in reliability and the broadening of their application fields, the nonvolatile semiconductor storage devices have become used for data recording purposes involving filesystems, which need frequent write and erase operations, similarly to the way the magnetic storage devices are used. Further, since the data to be handled by nonvolatile semiconductor storage devices has become large in scale, as typified by audio data, write and erase operations have become more frequently implemented in succession.
For the above reasons, the redundancy of operations when write or erase commands are input in succession, i.e., restarting pumping after once turning the charge pump circuit off, can be no longer disregarded. More specifically, the control method of the conventional nonvolatile semiconductor storage devices suffers the problem of increased total time for writing or erasing and increased power consumption.
Under such circumstances, there have been demands for a method which is capable of omitting part of the internal operation that becomes redundant when write or erase commands are input in succession, by providing a means of distinguishing the types of commands input in row and hence can reduce the time of write and/or erase operations and cut down the power consumption.
The present invention has been devised under the above circumstances, it is therefore an object of the present invention to provide a nonvolatile semiconductor storage device and its control method, wherein the time required for write or erase operations to be implemented in succession can be cut down.
In order to achieve the above object, the nonvolatile semiconductor storage device and its control method of the present invention are configured as follows:
In accordance with the first aspect of the present invention, a nonvolatile semiconductor storage device includes: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; and a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array, and is characterized in that the command user interface includes a successive command input detecting means for detecting the successive inputs of commands of the same type, and when the successive command input detecting means detects commands of the same type in succession, the write and erase control circuit functions so as to control the internal operations by skipping part of the sequence of the internal operations constituting the input, first command operation and starting execution of the second command before the first command has been completed.
In accordance with the second aspect of the present invention, the nonvolatile semiconductor storage device having the above first feature is characterized in that the successive command input detecting means of the command user interface comprises: a storage means for storing the type of an input command; a comparing means for comparing the type of a command input next to that of the stored command; and an output means for outputting the comparison result in the comparing means.
In accordance with the third aspect of the present invention, the nonvolatile semiconductor storage device having the above first feature is characterized in that the externally input commands are made up of multiple cycles, and comparison by the command user interface between the first and second commands as to command type is carried out during the first cycle of the second command.
In accordance with the fourth aspect of the present invention, the nonvolatile semiconductor storage device having the above second feature is characterized in that the externally input commands are made up of multiple cycles, and comparison by the command user interface between the first and second commands as to command type is carried out during the first cycle of the second command.
In accordance with the fifth aspect of the present invention, a control method of a nonvolatile semiconductor storage device comprising: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; and a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array, wherein the command user interface includes a successive command input detecting means for detecting the successive inputs of commands of the same type, and when the successive command input detecting means detects commands of the same type in succession, the write and erase control circuit functions so as to control the internal operations by skipping part of the sequence of the internal operations constituting the input, first command operation and starting execution of the second command before the first command has been completed, includes: the first step of activating the charge pump circuit for pumping the output voltage therefrom to a predetermined voltage; the second step of setting the threshold voltage of the memory cell transistor at a predetermined level, by applying the pumping voltage generated at the first step; and the third step of deactivating the operation of the charge pump circuit so as to restore the output voltage to the initial state, and is characterized in that when the second command being input during implementation of the first command is of the same type as that of the first command, the second step of the execution of the second command is started following the end of the second step of the execution of the first command.
In accordance with the sixth aspect of the present invention, a nonvolatile semiconductor storage device includes: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array; and a means for receiving a successive operation control signal which indicates that a command of the same type as that of the preceding command has been externally input in succession, and is characterized in that the write and erase control circuit distinguishes the status of the successive operation control signal, and when the successive operation control signal is active, the write and erase control circuit functions so as to control the internal operations by skipping part of the sequence of the internal operations constituting the input, first command operation and starting execution of the second and following commands input in succession before the preceding command has been completed.
In accordance with the seventh aspect of the present invention, the nonvolatile semiconductor storage device having the above sixth feature further includes a dedicated external terminal through which the successive operation control signal is supplied.
In accordance with the eighth aspect of the present invention, the nonvolatile semiconductor storage device having the above sixth feature further includes a means for generating the successive operation control signal from the chip-select signal input externally.
In accordance with the ninth aspect of the present invention, a control method of a nonvolatile semiconductor storage device comprising: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array; and a means for receiving a successive operation control signal which indicates that a command of the same type as that of the preceding command has been externally input in succession, wherein the write and erase control circuit distinguishes the status of the successive operation control signal, and when the successive operation control signal is active, the write and erase control circuit functions so as to control the internal operations by skipping part of the sequence of the internal operations constituting the input, first command operation and starting execution of the second command and following commands input in succession before the preceding command has been completed, includes: the first step of activating the charge pump circuit for pumping the output voltage therefrom to a predetermined voltage; the second step of setting a threshold voltage of the memory cell transistor at the predetermined level, by applying the pumping voltage generated at the first step; and the third step of deactivating the operation of the charge pump circuit so as to restore the output voltage to the initial state, and is characterized in that when the successive operation control signal is active, the second step of the execution of the second command is started following the end of the second step of the execution of the first command.
In accordance with the tenth aspect of the present invention, a nonvolatile semiconductor storage device includes: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array; and a timer circuit, and is characterized in that the write and erase control circuit has the function of setting the count time in the timer circuit and controlling the count start, and the timer circuit has the function of controlling the activation and deactivation of the operation of the charge pump circuit.
In accordance with the eleventh aspect of the present invention, the nonvolatile semiconductor storage device having the above tenth feature is characterized in that in the timer circuit the count time of waiting for a command of the same type to be externally input in succession can be adjusted arbitrarily.
In accordance with the twelfth aspect of the present invention, a control method of a nonvolatile semiconductor storage device comprising: a memory cell array made up of a multiple number of nonvolatile memory cells; a charge pump circuit for generating voltages for data writing and erasing of memory cells; a command user interface for interpreting a command externally input and generating a signal instructing execution of the command; a write and erase control circuit which receives the signal from the command user interface and controls a series of internal operations constituting writing and erasing of data in the memory cell array so as to supply the voltage generated by the charge pump circuit to the memory cell array; and a timer circuit, wherein the write and erase control circuit has the function of setting the count time in the timer circuit and controlling the count start, and the timer circuit has the function of controlling the activation and deactivation of the operation of the charge pump circuit, includes: the first step of activating the charge pump circuit to pumping the output voltage therefrom to a predetermined voltage; the second step of setting the threshold voltage of the memory cell transistor at a predetermined level, by applying the pumping voltage generated at the first step; and the third step of deactivating the operation of the charge pump circuit so as to restore the output voltage to the initial state, and is characterized in that when the second command is input while the timer circuit, which starts counting from the end of the second step of the execution of the first command, is counting up to the predetermined count time, the second step of the execution of the second command is started following the end of the second step of the execution of the first command.
According to the configuration of the present invention, it is possible to distinguish that successive commands of the same type, for example, successive write commands, have been input, so that redundant internal operations such as deactivation and restarting of the charge pump circuit, which would take place when successive commands have been input, can be avoided based on the determined result.
According to the configuration of the present invention, it is possible to determine whether the first command and the second command input subsequently is of the same type.
According to the configuration of the present invention, the type of the second command input subsequently can be determined from the first cycle of the command only. Therefore, the time required for the determination can be shortened hence the total operation time in the successive mode can be further cut down.
According to the configuration of the present invention, it is possible to omit deactivation and restarting of the charge pump circuit, which would take up much time when successive operations are to be made. Therefore, it is possible to markedly reduce the total operation time in the successive operation mode.
According to the configuration of the present invention, it is possible to readily identify the status in which successive commands of the same type, for example, successive write commands, have been input, so that redundant internal operations such as deactivation and restarting of the charge pump circuit, which would take place when successive commands have been input, can be avoided based on the determined result.
According to the configuration of the present invention, it is possible to obtain the successive operation control signal in a markedly simple manner.
According to the configuration of the present invention, it is possible to obtain the successive operation control signal without the necessity of any modification of the external terminal specifications of the conventional configuration.
According to the configuration of the present invention, it is possible to omit deactivation and restarting of the charge pump circuit, which would take up much time when successive operations are to be made. Therefore, it is possible to markedly reduce the total operation time in the successive operation mode.
According to the configuration of the present invention, when successive commands of the same type have been input within a certain fixed period of time, it is possible to readily avoid redundant internal operations such as deactivation and restarting of the charge pump circuit, which would take place in the successive operation mode.
According to the configuration of the present invention, it is possible to arbitrarily set the interval, based on which commands of the same type are input in succession.
According to the configuration of the present invention, when the interval of commands of the same type being input in succession is predetermined, it is possible to readily omit redundant deactivation and restarting of the charge pump circuit, which would take up much time when successive operations are to be made. Therefore, it is possible to markedly reduce the total operation time in the successive operation mode.